1. Field of the Invention
The present invention relates to a method of operating a semiconductor memory device, and more particularly, to a method of operating a Phase Random Access Memory (PRAM).
2. Description of the Related Art
PRAMs are nonvolatile memory devices such as flash memories, ferroelectric RAMs (FeRAMs), magnetic RAMs (MRAMs), and the like. A structural difference between PRAMs and other nonvolatile memory devices is in a storage node.
Exemplary PRAMs include a phase change layer whose phase is changed from an amorphous state into a crystal state at a predetermined temperature. A resistance of the phase change layer is high in the amorphous state but low in the crystal state. Such PRAMs write and read bit data using such a resistance characteristic of the phase change layer.
FIG. 1 is a view illustrating a conventional PRAM. Referring to FIG. 1, the conventional PRAM includes a transistor Tr and a storage node 10. The storage node 10 includes a lower electrode 10a, a phase change layer 10c, an upper electrode 10d, and a conductive plug 10b connecting the phase change layer 10c to the lower electrode 10a. The lower electrode 10a of the storage node 10 is connected to the drain of the transistor Tr.
FIG. 2 is a view illustrating a method of operating the conventional PRAM. Referring to FIG. 2, when a phase of the phase change layer 10c is in a crystal state (this state is generally regarded as bit data “0” is written), a first phase change current Irs is applied from the upper electrode 10d through the conductive plug 10b to the lower electrode 10a. The first phase change current Irs is called a reset current. The first phase change current Irs is a pulse current and has a lasting time or duration of about 30 ns and has amperage of about 1.6 mA. Since a width of the conductive plug 10b is considerably narrower than that of the phase change layer 10c, the first phase change current Irs concentrates on an area A1 of the phase change layer 10c contacting the conductive plug 10b. Thus, a temperature of the area A1 abruptly becomes higher than or equal to a phase change temperature. As a result, a phase of the area A1 of the phase change layer 10c is changed from a crystal state into an amorphous state. When the area A1 of the phase change layer 10c is in the amorphous state as described above, bit data “1” is generally regarded as being written to the PRAM.
When the area A1 of the phase change layer 10c is in the amorphous state as shown in the central illustration of FIG. 2, a second phase change current Is is applied to the storage node 10 in a direction along which the first phase change current Irs has been applied. The second phase current Is is called a set current. The second phase current Is is also a pulse current. A duration of the second phase change current Is is longer than the duration of the first phase change current Irs while the amperage of the second phase change current Is is smaller than that of the first phase change current Irs. For example, the duration of the second phase change current Is is about 180 ns and the amperage of the second phase change current Is is smaller than that of the first phase change current Irs. While the second phase change current Is is applied, the area A1 of the phase change layer 10c is changed from the amorphous state into the crystal state.
As described above, in a case of the conventional PRAM, a state of the phase change layer 10c is determined by the first and second phase change currents Irs and Is applied from the upper electrode 10d through the conductive plug 10b toward the lower electrode 10a. However, the first phase change current Is, i.e., the reset current, applied to the phase change layer 10c to change a state of the area A1 of the phase change layer 10c into the amorphous state is an obstacle to the improvement of the characteristic of the conventional PRAM. For example, it is not difficult to reduce sizes of the storage node 10 and the transistor Tr to reduce a size of the conventional PRAM with the development of a technique for fabricating semiconductors. However, a current that the transistor Tr can accommodate, i.e., amperage allowed to pass through the transistor Tr, is reduced with the reduction in the size of the transistor Tr. When the size of the transistor Tr is reduced, the transistor Tr cannot accommodate the amperage, 1.6 mA, of the first phase change current Irs. Thus, if the first phase change current Irs is not reduced, it is difficult to highly integrate the PRAM.